The present invention relates generally to a power MOSFET, and more particularly, to a process for forming a trench power MOSFET with improved voltage endurance and reduced parasitic capacitance thereof.
One type of semiconductor devices formes their gates in a trench, such as trench-gate MOSFET, integrated gate bipolar transistor (IGBT), junction field effect transistor (JFET), and accumulated field effect transistor (ACCUFET). These trench devices have a common characteristic that the structure formed in the trench is exposed to high electric field and the insulator at the bottom of the trench results in effective parasitic capacitance, and these effects restrict the devices shrinked.
The power MOSFET has already been widely used for example in switching power supply (SPS). In modern applications, lower gate charge, higher cell density and lower price are essential requirements for the power MOSFET. Unfortunately, as in the forgoing description, the high electric field the structure in the trench endured and the parasitic capacitance resulted from the insulator restrict the increasing of cell density. Special process and MOSFET structure can be used to increase the cell density but it will also increase manufacture cost. Therefore, power MOSFET with low cost, high cell density and low ON resistance is one of the goal for those who skilled in the art. Williams et al. disclosed a process for trench semiconductor devices in U.S. Pat. Appli. No. 20010026961 to form a thick gate oxide at the bottom of the trench to increase the endurance in high electric field and reduce the parasitic capacitance. However, in this art, to form the thick gate oxide at the bottom of the trench, etching the thick gate oxide is easy to damage the sidewall of the trench and as a result, induces unpredictable effects, such as larger leakage current and easier punch-through at the gate sidewall in the resulted MOSFET. It is therefore desired further improved process.
An object of the present invention is to provide a process for trench power MOSFET with low gate charge, high cell density and low cost. A process for trench power MOSFET comprises, according to the present invention, forming a trench on a semiconductor substrate and then forming a first oxide, a nitride and a second oxide in the trench that are further etched to remain a part of them at the bottom of the trench before subsequently fabricating the other structure of the power MOSFET. By the inventive process, a thick insulator is formed at the bottom of the trench to improve the endurance of the power MOSFET in high electric field and reduce the parasitic capacitance of the power MOSFET, and thereby the cell density is increased. Particularly, the nitride in the inventive process protects the sidewall of the trench from damages during the formation of the thick oxide at the bottom of the trench by etching the second oxide.